Efficient FPGA implementation of high-throughput mixed radix multipath delay commutator FFT processor for MIMO-OFDM

This article presents and evaluates pipelined architecture designs for an improved high-frequency Fast Fourier Transform (FFT) processor implemented on Field Programmable Gate Arrays (FPGA) for Multiple Input Multiple Output Orthogonal Frequency Division Multiplexing (MIMO-OFDM). The architecture presented is a Mixed-Radix Multipath Delay Commutator. The presented parallel architecture utilizes fewer hardware resources compared to Radix-2 architecture, while maintaining simple control and butterfly structures inherent to Radix-2 implementations. The high-frequency design presented allows enhancing system throughput without requiring additional parallel data paths common in other current approaches, the presented design can process two and four independent data streams in parallel and is suitable for scaling to any power of two FFT size N. FPGA implementation of the architecture demonstrated significant resource efficiency and high-throughput in comparison to relevant current approaches within literature. The proposed architecture designs were realized with Xilinx System Generator (XSG) and evaluated on both Virtex-5 and Virtex-7 FPGA devices. Post place and route results demonstrated maximum frequency values over 400 MHz and 470 MHz for Virtex-5 and Virtex-7 FPGA devices respectively

A new approach to pipeline FFT processor

A new VLSI architecture for a real-time pipeline FFT processor is proposed. A hardware-oriented radix-22 algorithm is derived by integrating a twiddle factor decomposition technique in the divide-and-conquer approach. The radix-22 algorithm has the same multiplicative complexity as the radix-4 algorithm, but retains the butterfly structure of the radix-2 algorithm. The single-path delay-feedback architecture is used to exploit the spatial regularity in the signal flow graph of the algorithm. For length-N DFT computation, the hardware requirement of the proposed architecture is minimal on both dominant components: log4N-1 complexity multipliers and N-1 complexity data memory. The validity and efficiency of the architecture have been verified by simulation in the hardware description language VHDL

Design and implementation of a 1024-point pipeline FFT processor

pipeline FFT processor is presented. The architecture is based on a new form of FFT, the radi~-2 ~ algorithm. By exploiting the spatial regularity of the new algorithm, minimal requirement for both dominant components in PLSI implementation has been achieved: only 4 complex multipliers and 1024 complex-word data memory for the pipelined 1K FFT processor. The chip has been implement in OSp CMOS technology and takes an area of 40 mm’. With 3.3 ~ power supply, it can compute 2n, n = 0, 1,..., 10 complex point forward and inverse FFT in real time with up to 30MHz sampling frequency. The SQNR is above 50dB for white noise input. I

Designing pipeline FFT processor for OFDM (de)modulation

The FFT processor is one of the key components in the implementation of wideband OFDM systems. Architectures with a structured pipeline have been used to meet the fast, real-time processing demand and low-power consumption requirement in a mobile environment. Architectures based on new forms of FFT, the radix-2i algorithm derived by cascade decomposition, is proposed. By exploiting the spatial regularity of the new algorithm, the requirement for both dominant elements in VLSI implementation, the memory size and the number of complex multipliers, have been minimized. Progressive wordlength adjustment has been introduced to optimize the total memory size with a given signal-to-quantization-noise-ratio (SQNR) requirement in fixed-point processing. A new complex multiplier based on distributed arithmetic further enhanced the area/power efficiency of the design. A single-chip processor for 1 K complex point FFT transform is used to demonstrate the design issues under consideration

Research of Optimal Experiment on Bridge Pier Types for Reducing Backwater

There are many kinds of commonly-used bridge pier types. This paper researches the selection principle and optimal type of the bridge pier types from the perspective of reducing backwater. This paper also tests and analyzes the high resistance water for different types of bridge pier under different flow velocities and conditions of water resistance ratio through establishment of a physical model of wide water channel. The result shows that, the bridge pier has an optimal profile curve, and the characteristic parameter (b’/L) is from 0.071 to 0.083; three kinds of commonly-used pier types – square pier, streamline pier and bicircular pier have different strength angles. If the angle between the axis of bridge pier and the water flow direction is less than 36°, it should give priority to the streamline pier; if the angle is greater than 36°, then it should give priority to the bicircular pier

Wordlength Optimization of a Pipelined FFT Processor

This paper describes the optimization of the word lengths in an 8 k-points pipelined FFT processor. The word lengths can be freely chosen since the FFT is implemented as a full custom ASIC. According to the specification, input and output word lengths are 12 bits but improved performance on be achieved by using a longer wordlength internally. Increased wordlength means increased size, both for memory and arithmetic operations. Since the FFT processor uses large memories, especially in the early stages, it is especially important to keep wordlength short in the beginning of the pipeline. Finding a good trade-off between precision and size is a difficult problem and it is not reasonable to solve analytically. Simulations using a C-model are therefore used to find an acceptable solution. The simulations show that a good solution is obtained by starting with 12 bits and gradually increasing the wordlength up to 16 bits. The final result is rounded back to 12 bits. This is a good trade-off between precision and complexit

Response of Fresh Water Distributions on Abrupt Changes of Topography in the Pearl River Networks of China

A 2-D numerical model was used to study the response of fresh water transports and distributions on the abrupt changes of topography in the Pearl River Networks (RNPRD). The results indicate that both the tidal forces in Jiaomen and Humen and the runoff power in Modaomen are intensified, which leads to a fresh water movement from the northeast to the southwest side of the West and North River Delta Networks. However, the water distributions in the East River Delta Networks remain almost the same. The residual currents in the RNPRD decreased dramatically in the West and North River Delta Networks due to the increasing volume of the river channels. This decreasing trend was intensified in the North River Main Channel due to the annual water discharge redistribution in the RNPRD

Response of Fresh Water Distributions on Abrupt Changes of Topography in the Pearl River Networks of China

A 2-D numerical model was used to study the response of fresh water transports and distributions on the abrupt changes of topography in the Pearl River Networks (RNPRD). The results indicate that both the tidal forces in Jiaomen and Humen and the runoff power in Modaomen are intensified, which leads to a fresh water movement from the northeast to the southwest side of the West and North River Delta Networks. However, the water distributions in the East River Delta Networks remain almost the same. The residual currents in the RNPRD decreased dramatically in the West and North River Delta Networks due to the increasing volume of the river channels. This decreasing trend was intensified in the North River Main Channel due to the annual water discharge redistribution in the RNPRD

Research of Optimal Experiment on Bridge Pier Types for Reducing Backwater

There are many kinds of commonly-used bridge pier types. This paper researches the selection principle and optimal type of the bridge pier types from the perspective of reducing backwater. This paper also tests and analyzes the high resistance water for different types of bridge pier under different flow velocities and conditions of water resistance ratio through establishment of a physical model of wide water channel. The result shows that, the bridge pier has an optimal profile curve, and the characteristic parameter (b’/L) is from 0.071 to 0.083; three kinds of commonly-used pier types – square pier, streamline pier and bicircular pier have different strength angles. If the angle between the axis of bridge pier and the water flow direction is less than 36°, it should give priority to the streamline pier; if the angle is greater than 36°, then it should give priority to the bicircular pier